1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having high density and high operating speed.
2. Description of the Prior Art
In semiconductor integrated circuits, high integration density, high operating speed and low electric power consumption are being achieved. However, such devices have a problem regarding the area necessary for circuit wiring. Although it is impossible to eliminate wiring for signal propagation, the area required for wiring of the power supply always presents a problem. This is because the current flowing through the power supply line is generally large and is apt to be easily obstructed by an increase in wiring resistance due to crossovers and or the like.
In bipolar integrated circuits, there are many devices in which the collector regions are connected to a power supply, so that a significant advantage will be provided if the substrate can be used as a common power supply for these devices. However, in the actual device, a P-N junction is made between the substrate and collector region and it is impossible to fetch only the potential of selected collectors from the substrate.
On the other hand, in MOS integrated circuit devices, for example, in a memory circuit or the like, two kinds of values of V.sub.t (threshold voltages) such as zero threshold and the like are needed in one chip. As a method of providing two kinds of V.sub.t values, the impurity concentration in the channel region is changed by ion implantation or the like. However, if the V.sub.t value can be independently varied by a substrate bias applied from the outside, an optimum device can be realized and the wiring for the power supply can be also omitted.
On the other hand, in CMOS integrated circuits, although it is slightly difficult to realize high integration density, they have an excellent feature of low electric power consumption, so that they are being widely used. However, a large drawback of such a CMOS device is that a so called latch-up phenomenon occur with an increase in density, so that an excessive current flows and will finally result in breakdown of the device. As for this latch-up phenomenon, a thyristor which is parasitically defined is turned on due to some surge current from the outside, so that an excess current flows. Therefore, the current gain h.sub.FE of the parasitic transistor becomes larger as the distance between the devices becomes narrower and the latch-up can be easily caused. Thus, such a latch-up phenomenon will be a problem in the future. In particular, since latch-up ordinarily occurs due to external noise entering through the input and output, it can be prevented by paying attention to the input and output terminals, setting the distance to be large and setting the value of h.sub.FE to be small. However, in case of a small IC and a device having extremely large input and output terminals, such a method is unsuitable since the device area is merely enlarged in vain. Consequently, in CMOS circuits, it is demanded to prevent latch-up without increasing the area.
The second problem in a conventional CMOS circuit relates to the operating speed. Although the operating speed of an MOS transistor increases with a decrease in area, the MOS transistor is inherently a device which is driven by a voltage and the current changes such that its value is squared with respect to the voltage. Therefore, in a circuit having a small fan out, the operating speed is fairly high; however, in an ordinary LSI having a large fan out, there is a drawback such that the operating speed rapidly decreases. On this point, the V-I characteristic of the bipolar device changes like an exponential function, so that there is an advantage such that the operating speed does not decrease to the same extent even in an LSI having a large fan out.
In view of the above, it is preferred to integrally form CMOS and bipolar devices having their respective advantages. As a process which has already been disclosed, there is a publication of Zimmer et al, "IEEE Trans on Electron Devices", Vol. ED-26, No. 4, pages 390-396, April, 1982. The process relates to a method in the CMOS process whereby an npn transistor is formed using the N well region as a collector of a bipolar device. Although the method is simple, it has a drawback such that the collector resistance increases since no buried layer of the collector exists. Therefore, in the case of the device in which CMOS and bipolar devices are integrally formed, it is necessary that it has a buried layer of a low resistance. As mentioned above, the requirements needed as a process for integration of bipolar and CMOS devices are as follows:
1. to have a structure such that no latch-up occurs even when the device area is small; and
2. to set the collector resistance of the integrated bipolar transistor to be sufficiently low.